/*
	ARMada
	Fetch stage
*/

module fetch
(
	input clk,
	input rst,
	input cond,
	input [5:0] branch_r15,		//Where to branch address if condition...
	input [5:0] data,			//Data retrieved from memory (the instruction)

	output reg [5:0] address,	//Address to memory
	output reg read_enable,
	
	output reg [5:0] r15_buff,	//Program Counter output buffer
	output reg [5:0] ir_buff	//Instruction Register output buffer
);

reg [5:0] r15_buff_next;
reg [5:0] ir_buff_next;

reg [5:0] r15, r15_next;		//[Internal] R15 (PC)
reg [5:0] ir, ir_next;			//[Internal] Instruction Register

// descrierea registrelor de stare
always @(posedge clk or negedge rst)
begin: state_registers
  if (!rst)
	begin
		r15 <= 0;
		r15_buff <= 0;
		ir <= 0;
		ir_buff <= 0;
	end
  else
	begin
		r15 <= r15_next;
		r15_buff <= r15_buff_next;
		ir <= ir_next;
		ir_buff <= ir_buff_next;
	end
end

//descrierea logicii combinationale care calculeaza starea urmatoare
//si genereaza semnalele de control
always @(r15 or cond)
begin
	if (cond)
		r15_next = branch_r15;
	else
		r15_next = r15 + 4;
	r15_buff_next = r15_next;
	
	ir_next = data;
	ir_buff_next = ir_next;
	
	read_enable = 1'b1;
end
endmodule
